1. Field of the Invention
This invention relates generally to interlaced serial-parallel-serial charge-coupled memory devices, and more particularly, to a novel arrangement which outputs the serial data bit stream in the same original sequence as the input bit stream.
2. Description of the Prior Art
Interlaced serial-parallel-serial memory devices for use in data processing system storage and communication signal processing are well-known in the art. Referring to the patents and publications listed below under the heading "References Cited By Applicant", Boyle and Smith [Refs. 1, 2, 3] originally disclosed the basic charge-coupled concept. Weimer [Ref. 4], Tompsett [Ref. 5] and Collins [Ref. 6] disclosed serial-parallel-serial arrangements.
In the serial-parallel-serial configuration, a data bit stream is injected into a serial input shift register from where it is transferred in parallel to a parallel storage section. The data can then be shifted in parallel through the parallel section, and then transferred in parallel to a serial output register, from where it is shifted out as a serial bit stream.
This serial-parallel-serial configuration had bit density limitations because charge-coupled devices require both transfer and storage sites. That is, in a two-phase serial shift register, the storage of one bit of information requires not only a storage site but also a transfer site so that bits are actually stored at one instant of time in only one-half of the available sites. For example, in a two-phase serial charge-coupled device with eight sites, only four bits can be stored. The parallel section was similarly limited in that the channel width was necessarily twice the width of a single site in the serial sections so that only one-half of the potentially available storage sites in the parallel section could be utilized.
Bit storage density was then significantly improved by the interlaced modification of the serial-parallel-serial configuration. In an interlaced version of the above example having eight sites and two-phase operation, all eight serial bits can be transferred in parallel through the parallel section, at least theoretically doubling the number of bits that can be stored in the parallel section. Embodiments of interlaced configurations are disclosed by Elmer et al. [Ref. 10, 11, 12], Kosonocky [Ref. 8, 9], and Erb [Ref. 7].
However, the interlaced configuration of the prior art had the serious disadvantage that the data bits were scrambled upon transfer from the serial input register into the first row of the parallel section. That is, the data bits were put in a sequential order different from the original order of the input bit stream. It was then necessary to provide additional circuitry to unscramble the bits and put them back into the original sequential order. This additional circuitry substantially increased the complexity and cost of the interlaced devices.